(1) Technical Field
This invention relates to electronic circuits, and more particularly to voltage regulator circuits.
(2) Background
In electronic systems, particularly those systems having a single voltage supply, there is often a need in some part of the component circuitry for a voltage that is higher than the supply voltage; for example, a particular system may have a 4.5V power supply, but some portion of the component circuitry may need an 8V supply (an enhanced voltage). A conventional approach to supplying an enhanced voltage is to include in the system a switched capacitor voltage multiplier (sometimes called a charge pump), and then down-regulate the output voltage from the voltage multiplier to the desired output level.
For example, FIG. 1a is a circuit diagram of a prior art switched capacitor voltage doubler followed by a down-regulator circuit. FIG. 1b is a timing diagram of a two-phase clock signal 101 used in conjunction with the circuit shown in FIG. 1a. In the illustrated circuit, the input voltage Vin is doubled to approximately 2*Vin, then down regulated to Vout. In particular, a pump capacitor Cp 100 is first charged to Vin during phase 1 of the clock 101; during phase 1, the switches 102, 104 are in the position shown in FIG. 1a. During phase 2 of the clock 101, the switches 102, 104 are flipped so as to place pump capacitor Cp 100 in series with a holding capacitor C 106. This action adds the voltage from pump capacitor Cp 100 (approximately equal to Vin) in series with the voltage on the holding capacitor C 106 (which is also approximately equal to Vin in steady-state), creating a voltage V at the holding capacitor C 106 that is approximately double the input voltage Vin. Thereafter, a conventional linear regulator circuit 108 may be used to regulate V down to a desired value Vout (<2*Vin). An output capacitor Co 110 may be provided to filter voltage ripple out of Vout.
As an alternative to the linear regulator circuit 108, lossy switches (not shown) may be used to absorb surplus voltage in order to generate the desired value Vout by controlling the ON resistance of one or more lossy switches.
The phases of the clock signal 101 are distinct and preferably configured so that adjacent switches in FIG. 1a operate with proper phasing so as to charge and discharge the various capacitances as described above; there are multiple ways known in the art to achieve such a configuration.
The nominal efficiency of the prior art circuit shown in FIG. 1a is equal to Vout/(2*Vin), ignoring component losses. In cases where Vout is close to double the value of Vin, the conventional circuit approach shown in FIG. 1a is reasonably efficient. Thus, if Vout=8V, and Vin=4.5V, then the efficiency is 8/9, or about 89%.
However, there are often electronic systems where a desired Vout is only slightly higher than the Vin value (e.g., Vin=4.5V, Vout=5V). Thus, for the circuit shown in FIG. 1a, 1f Vout=5V and Vin=4.5V, then the efficiency is at best 5/9, or about 56%. This efficiency value is further reduced by circuit losses, resulting in an achievable efficiency that typically is less than 50%. Accordingly, in such cases, the prior art circuit shown in FIG. 1a results in very low efficiency, wasting power, often in systems where power savings are important (e.g., cell phones) or where excess generated heat is undesirable (e.g., set top boxes).
There is thus a need for a voltage regulator circuit for efficiently generating a slightly enhanced voltage from an input power supply. The present invention addresses this need.